DRAMs have a plurality of memory cells which are respectively connected to bit lines, via which the stored information may be read out. The bit lines are connected to read amplifiers. In a read amplifier the potentials of two bit lines which are complementary to each other are compared when a memory cell is read out. For this purpose, with the help of the respective word line, the memory cell to be read out is opened, i.e., connected to the bit line, so that the charge stored in the memory capacitor is distributed on the bit line and slightly changes its potential. In the read amplifier the potential which is increased or decreased in this way is compared to the potential of a complementary bit line whose potential is not changed by opening a word line. The potential difference between the two bit lines (and/or the two read amplifier inputs) measured within the read amplifier is increased by the read amplifier and written back into the memory cell after the amplification. In this so-called spreading of the bit line potentials, the potential difference between both bit lines is artificially increased. After deactivating the word line a sufficiently high charge quantity is stored again in the charge capacitor. Reading out is performed inside the memory in the read amplifier. The readout result may be passed on, for example, upon an explicit readout command. The readout result may also be written back into the memory cell for refreshing the same. Likewise, a new information may be written into the memory cell, irrespective of the data bits stored and read out previously. Here, the bit line potentials are spread according to the data bit to be stored.
In DRAMs, mainly two memory area-internal constructions regarding the arrangement of bit lines are known. In the folded bit line concept, the bit lines which are complementary to each other (i.e., to be spread against each other) pass along the same direction away from the read amplifier. In this construction a readout amplifier may often be connected to any one of two pairs of bit lines, for example, via a multiplexer, wherein two complementary bit lines of the same bit line pair respectively run towards each side.
In the open bit line concept, the complementary bit lines are directed in opposite directions away from the read amplifier to which they are connected. With both constructions, groups, each having a plurality of read amplifiers, are combined into rows of read amplifiers. These rows of read amplifiers generally run in parallel to each other, and the bit lines pass in a direction perpendicular to the course of the rows of read amplifiers away from the same. In the open bit line concept, the memory cells which are connected by two complementary bit lines lie on opposite sides of one of those rows of read amplifiers from which the bit lines originate. Accordingly, both bit lines respectively cross different groups of word lines. Thus, a capacitive crosstalk to the word line opening the memory cell to be read out only occurs at the active bit line; the complementary bit line experiences no comparative capacitive crosstalk. Thereby, at the active bit line a slight potential shift results which overlays the potential shift caused by the charge of the open memory cell, which should actually be read out. While semiconductor memories according to the folded bit line concept cause an equally strong coupling at both bit lines, semiconductor memories according to the open bit line concept are advantageous anyway regarding the lower substrate area consumption due to the higher packing density of memory cells below a base area of 8F2 (with the minimum structure width F).
Apart from the potential shift due to the coupling between the word line and the bit line, in particular crosstalk processes occur which are far more difficult to control which also influence the potential of a bit line to be read out. Thus, apart from the potential of the respectively adjacent bit line, in particular also the potential of the semiconductor substrate, the potential of a well arranged within the substrate, the potential of a common capacitor electrode of trench capacitors (buried plate) or also the common capacitor electrode of stacked capacitors (plate) may shift the bit line potential. All of those influences may cause readout errors in the read amplifier with an unfavorable influence on the bit line potential. There is thus the need, with volatile semiconductor memories, like, for example, DRAMs, in particular those in open bit line construction, to decrease the influences of parasitic capacitive or other influences on the potential of the bit lines.